1. Field of the Invention
The invention relates to a semiconductor process, and more particularly to a method for preventing alignment marks from disappearing after a chemical mechanical polishing (CMP) process.
2. Description of the Prior Art
Currently, in a semiconductor process, high overlap accuracy of optical aligner machines is quite important. In general, different optical aligner machines use different alignment approaches, with the ASML optical aligner machine being one of the more widely used in the semiconductor industry. Referring to FIG. 1, the principle of alignment used by the ASML optical aligner machine is to locate two alignment marks 10 which are disposed at two different locations of a wafer 11 using an optical approach. A cross-sectional view of an alignment mark 10 is shown in FIG. 2. Typically, the two alignment marks would not be destroyed in a front-end process, allowing the optical alignment to be readily accomplished. Furthermore, in the past, since no planarization step was executed in a back-end process, the alignment marks would not be harmed or removed. However, after chemical mechanical polishing processes were introduced into the semiconductor fabrication process, optical aligner machines could not easily locate the alignment marks, and in some cases, could not find the alignment marks at all, resulting in an alignment error or a non-alignment problem. A method for solving the above-mentioned problem according to the prior art will be described as follows.
First, referring to FIG. 3A, a dielectric layer 32 which is semi-transparent is deposited on a substrate 30 on which first alignment marks 31 are already formed so that second alignment marks 33 positioned directly over the first alignment marks 31 are formed on the dielectric layer 32. Referring to FIG. 3B, chemical mechanical polishing (CMP) is performed on the dielectric layer 32, resulting in the disappearance of second alignment marks 33. Referring to FIG. 3C, a first metal layer 34 is deposited on the dielectric layer 32 and then a first photoresist layer 35 is formed on the first metal layer 34 excepting that part of the first metal layer 34 over the first alignment marks 31. Referring to FIG. 3D, plasma etching is performed in order to form a first "metal clear out window" 301 over the first alignment marks 31, thereby exposing the first alignment marks 31 required for subsequent optical alignment of the first metal layer 34. Referring to FIG. 3E, a second photoresist 36 is formed on a part of the first metal layer 34. Referring to FIG. 3F, plasma etching is performed in order to form a desired metal pattern by removing a part of the first metal layer 34. Referring to FIG. 3G, a planarized dielectric layer 37 and second metal layer 38 are formed in order over the dielectric layer 32 and then a third photoresist 39 is formed on the second metal layer 38 excepting that part of the second metal layer 38 over the first alignment marks 31. Finally, referring to FIG. 3H, plasma etching is performed in order to form a required second "metal clear out window" 302 over the first alignment marks 31 by removing a part of the second metal layer 38 over the first alignment marks 31, thereby allowing the first alignment marks 31 to be exposed for use in subsequent optical alignment of the second metal layer 38. As is apparent from the above description, once a metal layer is deposited, extra photolithography and plasma etching processes are required in order to form a "metal clear out window", and thereby expose the alignment mark. However, this process is relatively complicated and requires a substantial amount of time for fabrication.